The past few decades have seen many shifts in electronics and semiconductor packaging that have impacted the entire semiconductor industry. The introduction of surface-mount technology (SMT), ball grid array (BGA), and land grid array (LGA) packages were generally important steps for high-throughput assembly of a wide variety of integrated circuit (IC) devices, while, at the same time, allowing reduction of the pad pitch on the printed circuit board. Conventionally packaged ICs have a structure basically interconnected by fine gold wire between metal pads on the die and electrodes spreading out of molded resin packages. Dual Inline Package (DIP) or Quad Flat Package (QFP) are fundamental structures of current IC packaging. However, increased pin count peripherally designed and arranged around the package typically results in too short of a pitch of lead wire, yielding limitations in board mounting of the packaged chip.
Chip-scale or chip-size packaging (CSP), BGA, and LGA are just some of the solutions that enable dense electrode arrangement without greatly increasing the package size. CSP provides for wafer packaging on a chip-size scale. CSP typically results in packages within 1.2 times the die size, which greatly reduces the potential size of devices made with the CSP material. Although, these advances have allowed for miniaturization in electronic devices, the ever-demanding trend toward even smaller, lighter, and thinner consumer products have prompted even further attempts at package miniaturization.
To fulfill market demands toward increased miniaturization and functionality, wafer-level CSP (WLCSP) has been introduced in recent years for generally increasing density, performance, and cost-effectiveness, while decreasing the weight and size of the devices in the electronic packaging industry. In WLCSP, the packaging is typically generated directly on the die with contacts provided by BGA or LGA. Recent advanced electronic devices, such as mobile phones, mobile computers, camcorders, personal digital assistants (PDAs), and the like, utilize compact, light, thin, and very densely packaged ICs. Using WLCSP for packaging smaller die size devices with lower numbers of pins, corresponding to larger number of chips on one wafer, is, therefore, usually advantageous and cost-effective.
One disadvantage of current WLCSP contact technology is the shape of the contact pillars formed between the wafer and the solder balls. According to the current WLCSP procedures, the contact pillar diameter will also be the final size for the solder ball pad. If it is discovered later in the manufacturing process that a larger-size solder ball drop will work better for the semiconductor device, the pillar diameter will be increased accordingly. This enlarging process not only increases the plating costs, it is also not generally a good solution for finer pitch pad design.
FIG. 1 is a cross-section view of die package 10. Die package 10 typically comprises wafer 100 and contact pillars 101 within insulating layer 101. Solder balls 103 are then printed, placed, or soldered onto the tops of each of contact pillars 101. If, later in the manufacturing process, it is realized that, instead of solder balls 103, larger-diameter solder balls, such as solder balls 104 (illustrated as the dotted line), should be used, insulating layer 102 will be etched with additional material plated into the etched sections to enlarge contact pillars 101 into contact pillars 105 (shown as dotted line). This enlarging process increases the manufacturing steps and the plating costs to create the larger contact pillars 105.
It should be noted that, for ease illustration, the larger solder ball and contact pillar were shown as dotted lines around only one of the noted features. In practice, each of the solder balls and contact pillars would be replaced with the enlarged version illustrated in the dotted line segments.